* (C) Copyright Efficient Power Conversion Corporation. All rights reserved.
*****************************************************************************
* Version History:
* 1.00: 04/26/2022 - Initial Model Creation
* 1.01: 08/14/2023 - Adapted for Simplis


.subckt EPC2066 gatein drainin sourcein
*#ASSOC Category=NMOS Symbol=nmos_sub mapping=2,1,3



.param  aWg={Wg*1E-3} Wg=4257000 A1={1.708e-02*aWg} k2=2.228e+00 k3=9.000e-02 rpara=3.050e-04
.param  si={aWg} so={aWg} sr={aWg}
+   rpara_s_factor=3.224e-01 aITc=4.200e-03 arTc=-5.184e-03 k2Tc=8.456e-04
+   x0_0=3.321e+00 x0_0_TC=-5.242e-03 x0_1=-2.000e-01 x0_1_TC=-1.000e-02
+   dgs1=4.3e-07 dgs2=2.6e-13 dgs3=0.8 dgs4=0.23
+   ags1={7.346e-13*si} ags2={3.054e-13*si} ags3=2.118e+00 ags4=2.319e-01
+   ags5={0.000e+00*si} ags6=7.480e+01 ags7=1.055e+01
+   agd1={3.641e-15*sr} agd2={1.374e-13*sr} agd3=-3.472e-01 agd4=4.414e+00
+   agd5={1.527e-14*sr} agd6=-1.348e+01 agd7=2.150e+00 agd8={0.000e+00*sr}
+   agd9=-3.326e+01 agd10=8.900e-01
+   asd1={3.249e-13*so} asd2={3.259e-13*so} asd3=-1.435e+01 asd4=1.899e+00
+   asd5={1.638e-13*so} asd6=-1.522e+01 asd7=6.350e+00 asd8={0.000e+00*so}
+   asd9=-8.125e+01 asd10=5.665e+00
+   rg_value=0.4

.model rpar res(TC1={-1.0*arTc} T_measured=25)
rd drainin  drain  rpar {(1-rpara_s_factor)*rpara}
rs sourcein source rpar {rpara_s_factor*rpara}
rg gatein gate {(rg_value)}

*Large resistors to aid convergence
Rcsdconv drain source {100000Meg/aWg}
Rcgsconv gate source {100000Meg/aWg}
Rcgdconv gate drain {100000Meg/aWg}

gswitch drain source Value {if(v(drain,source)>0,
+	(A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,source)-(k2*(1-k2Tc*(Temp-25))))/k3))*
+	v(drain,source)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,source))*v(drain,source)) ),
+	(-A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,drain)-(k2*(1-k2Tc*(Temp-25))))/k3))*
+	v(source,drain)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,drain))*v(source,drain)) ) )}

ggsdiode gate source VALUE {if( v(gate,source) < 10,
+	0.125*aWg/1077*(dgs1*(exp((v(gate,source))/dgs3)-1)+dgs2*(exp((v(gate,source))/dgs4)-1)),
+	0.125*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) }

ggddiode gate drain Value {if( v(gate,drain) < 10,
+	0.125*aWg/1077*(dgs1*(exp((v(gate,drain))/dgs3)-1)+dgs2*(exp((v(gate,drain))/dgs4)-1)),
+	0.125*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) }

*Gate-source capacitance
C_GS        gate source  {ags1}  TC=0,0
gC_CGS1     gate source Q={(0.5*ags2*ags4*log(1+exp((v(gate,source)-ags3)/ags4))+
+           ags5*ags7*log(1+exp((v(source,drain)-ags6)/ags7)) )}

*Gate-drain capacitance
C_GD        gate drain  {agd1}  TC=0,0
gC_CGD1     gate drain Q={(0.5*ags2*ags4*log(1+exp((v(gate,drain)-ags3)/ags4))+
+           agd2*agd4*log(1+exp((v(gate,drain)-agd3)/agd4))+
+           agd5*agd7*log(1+exp((v(gate,drain)-agd6)/agd7))+
+           agd8*agd10*log(1+exp((v(gate,drain)-agd9)/agd10)))}

*Source-drain capacitance
C_SD        source drain  {asd1}  TC=0,0
gC_CSD1     source drain Q={(asd2*asd4*log(1+exp((v(source,drain)-asd3)/asd4))+
+           asd5*asd7*log(1+exp((v(source,drain)-asd6)/asd7))+
+           asd8*asd10*log(1+exp((v(source,drain)-asd9)/asd10)) )}

.ends